# Computer Architecture 1) c = (a + b) /a d = b*(a + b) / a * c e = a* (c + d) Write the assembly to do the following statements for each of the following architectures. Use the least number of instructions. Reuse register when you can. (0,2) GPR (0,3) GPR (1,2) GPR (3,3) GPR 2) We have data stored in memory location 0x3aa, 0x3bb and 0x3cc. How do we perform the following operation multiply 0x3aa by 0x3bb and store into 0x3cc a) (3,3) GPU only using register indirect b) (3,3) GPU only using memory indirect (will need to have additional memory locations) 3) Write out how to solve the following code using any addressing mode for (0,3) GPR. Short a[50]; Int y,z; for( x=0; x<20; x++) { y = a[x + 3]; z = y + a[x%10]; } 4) How would you write good for A[x][y+5]? Use indirect addressing with index register. 5) Using only the register direct addressing modes write how to do the following CISC instruction ADD @(r1,r2),+(r4),80(r5)

1) To compute the equations c = (a + b) / a, d = b * (a + b) / a * c, and e = a * (c + d), we can use the following assembly instructions for each architecture:

a) (0,2) GPR:

add R2, R1 // R2 = a + b

div R2, R1 // R1 = (a + b) / a

mul R3, R2 // R3 = b * (a + b)

div R3, R1 // R1 = b * (a + b) / a

mul R4, R1 // R4 = (a + b) / a * c

mul R5, R1 // R5 = a * (c + d)

b) (0,3) GPR:

add R2, R1, R3 // R2 = a + b

div R2, R1 // R1 = (a + b) / a

mul R4, R1, R3 // R4 = b * (a + b)

div R4, R1 // R1 = b * (a + b) / a

mul R5, R1, R4 // R5 = (a + b) / a * c

mul R6, R1, R5 // R6 = a * (c + d)

c) (1,2) GPR:

add R2, R0, R1 // R2 = a + b

div R2, R0 // R0 = (a + b) / a

mul R3, R1 // R3 = b * (a + b)

div R3, R0 // R0 = b * (a + b) / a

mul R4, R0, R3 // R4 = (a + b) / a * c

mul R5, R0, R4 // R5 = a * (c + d)

d) (3,3) GPR:

add R2, R1, R0 // R2 = a + b

div R2, R0 // R0 = (a + b) / a

mul R3, R1, R0 // R3 = b * (a + b)

div R3, R0 // R0 = b * (a + b) / a

mul R4, R0, R3 // R4 = (a + b) / a * c

mul R5, R1, R4 // R5 = a * (c + d)

2) To multiply the values at memory location 0x3aa by 0x3bb and store the result in memory location 0x3cc, using different GPU architectures and addressing modes:

a) (3,3) GPU only using register indirect:

ldr r0, [0x3aa] // Load value at 0x3aa into r0

ldr r1, [0x3bb] // Load value at 0x3bb into r1

mul r0, r0, r1 // Multiply r0 by r1

str r0, [0x3cc] // Store the result in 0x3cc

b) (3,3) GPU only using memory indirect:

ldr r0, [0x3aa] // Load value at 0x3aa into r0

ldr r1, [0x3bb] // Load value at 0x3bb into r1

mul r0, r0, r1 // Multiply r0 by r1

ldr r2, [0x3cc] // Load current value at 0x3cc into r2

add r2, r0, r2 // Add r0 to r2

str r2, [0x3cc] // Store the result in 0x3cc

3) To solve the given code using any addressing mode for (0,3) GPR:

“`assembly

; Declare variables

a: .word 50 ; Array of 50 elements

y: .word 0 ; Initialize y to 0

z: .word 0 ; Initialize z to 0

x: .word 0 ; Initialize x to 0

; Main loop

loop:

cmp x, #20 ; Compare x with 20

bge end ; If x >= 20, exit loop

ldr r1, a ; Load base address of array a into r1

ldr r2, [r1, #12] ; Load a[x + 3] into r2 (r2 = a[x + 3])

ldr r3, [r1, r4] ; Load a[x % 10] into r3 (r3 = a[x % 10])

add r4, r4, #4 ; Increment r4 by 4 (r4 = r4 + 4)

add r5, r2, r3 ; Add r2 and r3 (r5 = y + a[x % 10])

str r2, y ; Store r2 into y (y = a[x + 3])

str r5, z ; Store r5 into z (z = y + a[x % 10])

add x, x, #1 ; Increment x by 1 (x = x + 1)

b loop ; Branch back to loop

end:

… ; Rest of the code

“`

4) To access the element A[x][y+5] using indirect addressing with an index register, we can use the following assembly code:

“`assembly

; Assuming A is a 2-dimensional array stored in memory starting at address A_base

; x and y are integers storing row and column indices

ldr r0, A_base ; Load base address of A into r0

add r1, r0, x ; Add x to r0 (r1 = A_base + x)

lsl r2, y, #2 ; Multiply y by 4 (assume each element is 4 bytes) and store the result in r2

add r3, r1, r2 ; Add r1 and r2 (r3 = A + x + 4y)

ldr r4, [r3] ; Load the value at address (A + x + 4y) into r4 (r4 = A[x][y+5])

“`

5) To perform the CISC instruction ADD @(r1,r2),+(r4),80(r5) using only register direct addressing modes, we can use the following assembly code:

“`assembly

ldr r6, [r1, r2] ; Load the value at address (r1 + r2) into r6

add r6, r6, r4 ; Add the value in r4 to r6

str r6, [r5, #80] ; Store the value in r6 at address (r5 + 80)

“`

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